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? freescale semiconductor, inc., 2004. all rights reserved. preliminary freescale semiconductor product brief s12hfampp rev. 11.1, 17-aug-2004 16-bit microcontroller hcs12h family introduction designed for automotive instrumentation applicat ions, all members of the mcs12h-family of microcontroller units (mcu) are composed of standar d on-chip peripherals including a 16-bit central processing unit (cpu12), up to 256k bytes of flash eeprom or rom, up to 12k bytes of ram, up to 4k bytes of eeprom on flash parts, one or two asynchr onous serial communications interfaces (sci), a serial peripheral interface (spi), an iic-bus interfac e (iic), an 8-channel 16-bit timer (tim), a 16-channel, 10-bit analog-to-digital converter (adc), up to si x-channel pulse width modulator (pwm), and up to two can 2.0 a, b software compatible modules. in addition , they feature a 32x4 liquid crystal display (lcd) controller/driver and a motor pulse width modulator (mc) consisting of up to 24 high current outputs suited to drive up to six stepper motors, and on selected devi ces, up to four stepper stall detectors (ssd) to simulataneously calibrate the pointer reset position of each motor. the mcs12h-family has full 16-bit data paths throughout. the inclusion of a pll circuit allows power consumpti on and performance to be adjusted to suit operational requirements. in addition to the i/o ports available in each module, up to 14 i/o ports are available with key-wake -up capability from stop or wait mode.
16-bit microcontr oller hcs12h family, rev. 11.1 2 freescale semiconductor preliminary feature detail feature detail note not all features listed here are available in all configurations. for a quick overview refer to table 1 . ? hcs12 core ? hcs12 16-bit cpu ? upward compatib le with m68hc11 instruction set ? interrupt stacking and programmer?s model identical to m68hc11 ? instruction queue ? enhanced indexed addressing ? hcs12 mebi (multiplexed expanded bus interface) ? hcs12 mmc (module mapping control) ? hcs12 int (interrupt control) ? hcs12 bkp (on-chip breakpoints) ? hcs12 bdm (single-wire background debug? mode) ? memory options ? 32k, 64k, 128k, 256k byte flash eeprom or 64k, 128k, 192k and 256k byte rom ? 2k, 4k, 6k, 8k, 12k byte ram ? 2k, 4k byte eeprom on flash versions only ? 8-bit and 4-bit ports with interrupt capability ? digital filtering ? programmable rising or falling edge trigger ? clock reset generator (crg) ? low current colpitts or pierce oscillator (0.5 to 16mhz reference clock) ? phase-locked loop clock frequency multiplier ? windowed cop watchdog and clock monitor resets ? real time interrupt ? up to 16-channels analog-to-digital converter (adc) ? 10-bit resolution ? external conversion trigger capability ? up to two 1m bit per second, can 2.0 a, b software compatible modules (mscan12) ? five receive and three transmit buffers ? flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit ? four separate interrupt channels for rx, tx, error and wake-up ? low-pass filter wake-up function ? loop-back for self test operation ? timer (tim) ? 16-bit main counter with 7-bit prescaler ? eight programmable input capture or output compare channels ? two 8-bit or one 16-bit pulse accumulators ? up to six pulse width modulator (pwm) channels
feature detail 16-bit microcontr oller hcs12h family, rev. 11.1 freescale semiconductor 3 preliminary ? programmable period and duty cycle for each channel ? pairs of 8-bit channels can be concatenated as one 16-bit channel ? center-aligned or left-aligned outputs ? wide range of programmable clock frequencies ? fast emergency shutdown input ? serial interfaces ? up to two asynchronous serial communications interfaces (sci) ? synchronous serial peripheral interface (spi) ? inter-ic bus interface (iic) ? liquid crystal display (lcd) driver ? up to 32 frontplanes and 4 backplanes ? 5 modes of operation allow for different di splay sizes to meet application requirements ? programmable frame clock generator and bias voltage level ? 16 or 24 high current drivers suited for pwm motor control ? each pwm channel switchable between two drivers in an h-bridge configuration ? support for sine and cosine drive ? 11-bit resolution with selectable dithering function ? left, right or center aligned outputs ? slew rate control ? up to four stepper stall detectors (ssd) - available on selected devices ? flexible full step and polarity set up to return the pointer to its reset position in clockwise or counter clockwise direction. ? integrator/sigma delta converter circuit to measure the induced voltage by the back emf of unpowered coil during full step (only one of the two motor coils is powered) operation. ? 16-bit down counter to monitor blanking and in tegration time to support stepper motors with different gear ratios. ? 16-bit accumulator register to read integratio n value, compare to a threshold at the end of integration time, and decide if the motor is st alled under this value or moving above this value. ? operating frequency ? 32mhz equivalent to 16mhz bus speed (only 9S12H256) ? 50mhz equivalent to 25mhz bus speed (except 9S12H256) ? 80-pin, 112-pin or 144-pin qfp package ? i/o lines with 5v i nput and drive capability ? 5v a/d converter inputs
16-bit microcontr oller hcs12h family, rev. 11.1 4 freescale semiconductor preliminary feature detail ? flash emulation of rom versions ? rom versions 3s12hz256, 3s12hz192, 3s12hz128 and 3s12hn128 should use the 9s12hz256 for flash emulation. ? rom versions 3s12hz64, 3s12hn64, 3s12hz32 and 3s12hn32 should use the 9s12hz64 for flash emulation. ? pin out explanations: ? a/d is the number of a/d channels. ? pwm is the number of tim channels. ? lcd denotes the number of front planes times the number of back planes. ? motor denotes the number of high current drive pins / number of stepper motors which can be driven ? ssd denotes whether this device features a stepper stall detection circuit ? versions with one sci will use sci0 ? versions with one can will use can0 ? i/o is the sum of ports capable to act as digital input or output. 144 pin package: port a = 8, b = 8, e = 6 + 2 input only, h = 8, j = 4, k = 5, l = 8, m = 6, p = 6, s = 8, t = 8, u = 8, v = 8, w = 8, pad = 16 input only. 14 inputs provide interrupt capability (h = 8, j = 4, irq, xirq). 112 pin package for h versions: port a = 8, b = 8, e = 6 + 2 input only, k = 5, l = 4, m = 4, p = 2, s = 6, t = 8, u = 8, v = 8, w = 8, pad = 8 input only. table 1 list of mcs12h-family members flash rom ram eeprom device package can sci spi iic a/d pwm tim lcd motor ssd kwu i/o 256k 0 12k 4k 9S12H256 144 lqfp 2 2 1 1 16 6 8 32x4 24/6 0 12 117 256k 0 12k 4k 9S12H256 (1) notes: 1. not recommended for new designs. 112 lqfp 2 1 1 0 8 2 8 28x4 24/6 0 0 85 128k 0 6k 2k 9s12h128 (1) 112 lqfp 2 1 1 0 8 2 8 28x4 24/6 0 0 85 256k 0 12k 2k 9s12hz256 112 lqfp 2 2 1 1 16 6 8 32x4 16/4 4 8 85 128k 0 6k 2k 9s12hz128 112 lqfp 2 2 1 1 16 6 8 32x4 16/4 4 8 85 64k 0 4k 1k 9s12hz64 112 lqfp 1 1 1 0 8 4 8 24x4 16/4 2 8 69 64k 0 4k 1k 9s12hn64 112 lqfp 0 1 1 0 8 4 8 24x4 16/4 2 8 69 64k 0 4k 1k 9s12hz64 80 qfp 1 1 0 0 7 4 4 20x4 16/4 2 7 60 64k 0 4k 1k 9s12hn64 80 qfp 0 1 0 0 7 4 4 20x4 16/4 2 7 60 0 256k 12k 0 3s12hz256 112 lqfp 2 2 1 1 16 6 8 32x4 16/4 4 8 85 0 192k 8k 0 3s12hz192 112 lqfp 2 2 1 1 16 6 8 32x4 16/4 4 8 85 0 128k 6k 0 3s12hz128 112 lqfp 1 2 1 1 8 6 8 32x4 16/4 4 8 85 0 128k 6k 0 3s12hn128 112 lqfp 0 2 1 1 8 6 8 32x4 16/4 4 8 85 0 64k 4k 0 3s12hz64 112 lqfp 1 1 1 0 8 4 8 24x4 16/4 2 8 69 0 64k 4k 0 3s12hn64 112 lqfp 0 1 1 0 8 4 8 24x4 16/4 2 8 69 0 32k 2k 0 3s12hz32 80 qfp 1 1 0 0 7 4 4 20x4 16/4 2 7 60 0 32k 2k 0 3s12hn32 80 qfp 0 1 0 0 7 4 4 20x4 16/4 2 7 60
feature detail 16-bit microcontr oller hcs12h family, rev. 11.1 freescale semiconductor 5 preliminary 2 inputs provide interrupt capability (irq, xirq). 112 pin package for 9hz256, 9hz128, 3hz128 and 3hn128 versions: port a = 8, b = 8, e = 6 + 2 input only, k = 5, l = 8, m = 5, p = 6, s = 6, t = 8, u = 8, v = 8, pad = 8. 10 inputs provide interrupt capability (ad = 8, irq, xirq). 112 pin package for 9hz64, 9hn64, 3hz64 and 3hn64 versions: port a = 8, b = 4, e = 4 + 1 input only, k = 5, l = 4, m = 2, p = 4, s = 5, t = 8, u = 8, v = 8, pad = 8. 9 inputs provide interrupt capability (ad = 8, xirq). 80 pin package for 9hz64, 9hn64, 3hz32 and 3hn32 versions: port a = 8, b = 4, e = 4 + 1 input only, k = 5, m = 2, p = 4, s = 5, t = 4, u = 8, v = 8, pad = 7. 8 inputs provide interrupt capability (ad = 7, xirq). ? compatibility considerations ? pins associated with motors 0 and 5 should be left unconnected to ensure compatibility with versions featuring 4 motors.
16-bit microcontr oller hcs12h family, rev. 11.1 6 freescale semiconductor preliminary block diagram block diagram figure 1. mc9s12h-family block diagram extal xtal bkgd xirq periodic interrupt cop watchdog clock monitor breakpoints pll xfc irq eclk pa4 pa3 pa2 pa1 pa0 pa7 pa6 pa5 test pb4 pb0 pb7 pb6 fp4 fp3 fp2 fp1 fp0 fp7 fp6 pe4 pe5 pe6 pe0 pe1 ioc2 ioc6 ioc0 ioc7 ioc1 ioc3 ioc4 ioc5 rxd0 txd0 miso mosi ps4 ps5 ps0 ps1 pulse width modulator pw2 pw0 pw1 pw3 pw4 pw5 pp3 pp4 pp5 pp0 pp1 pp2 pk3 pk7 pk0 pk1 sck ss ps6 ps7 spi rxcan0 txcan0 pm2 pm3 pin kwh2 kwh6 kwh0 kwh7 kwh1 kwh3 kwh4 kwh5 ddra ddrb pta ptb ddre pte ptk ddrk ptp ddrp pts ddrs ptm ddrm pk2 interrupt logic fp12 fp11 fp10 fp9 fp8 fp15 fp14 bp0 bp1 bp2 bp3 fp23 pl3 pl2 pl1 pl0 ddrl ptl fp19 fp18 fp17 fp16 pe7 pe3 pte ddre pe2 fp22 fp21 fp20 vlcd vlcd m0c0m m0c0p pu0 pu1 ptu ddru pwm0 motor0 lcd sci0 can0 modb moda reset vddpll vsspll cpu12 clock and reset generation module ptk ddrk fp13 pb5 pb3 pb2 pb1 fp5 pix0 pix1 pix2 pix3 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 fp24 fp25 fp26 fp27 an02 an06 an00 an07 an01 an03 an04 an05 pad03 pad04 pad05 pad06 pad07 pad00 pad01 pad02 vrh vrl an10 an14 an08 an15 an09 an11 an12 an13 pad11 pad12 pad13 pad14 pad15 pad08 pad09 pad10 vdda vssa analog to digital converter ptad vrh vrl vdda vssa kwj2 kwj0 kwj1 kwj3 128k, 256k bytes flash or rom 2k, 4k bytes eeprom 6k, 12k bytes ram multiplexed address/data bus ppage data15 motor0 and motor1 supply vddm1 vssm1 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 data7 data6 data5 data4 data3 data2 data1 data0 multiplexed wide bus multiplexed narrow bus ecs /romctl xaddr14 xaddr15 xaddr16 xaddr17 noacc/xclks lstrb /taglo r/w vddr vdd1 vss1,2 voltage regulator input capture and output compare timer sda scl pm0 pm1 iic vddx1,2 vssx1,2 vsspll pll 2.5v i/o driver 5v a/d converter 5v & vddpll vdd1 vss1,2 internal logic 2.5v vdda vssa vddr vreg input 5v supply pins driver pl7 pl6 pl5 pl4 fp31 fp30 fp29 fp28 voltage regulator reference system integration module single-wire background debug module rxd1 txd1 ps2 ps3 sci1 rxcan1 txcan1 pm4 pm5 can1 m0c1m m0c1p pu2 pu3 pwm1 m1c0m m1c0p pu4 pu5 pwm2 motor1 m1c1m m1c1p pu6 pu7 pwm3 m2c0m m2c0p pv0 pv1 ptv ddrv pwm4 motor2 motor2 and motor3 supply vddm2 vssm2 m2c1m m0c1p pv2 pv3 pwm5 m3c0m m3c0p pv4 pv5 pwm6 motor3 m3c1m m3c1p pv6 pv7 pwm7 m4c0m m4c0p pw0 pw1 ptw ddrw pwm8 motor4 motor4 and motor5 supply vddm3 vssm2 m4c1m m4c1p pw2 pw3 pwm9 m5c0m m5c0p pw4 pw5 pwm10 motor5 m5c1m m5c1p pw6 pw7 pwm11 pins shown in bold are not avail- able in the 112 qfp
block diagram 16-bit microcontr oller hcs12h family, rev. 11.1 freescale semiconductor 7 preliminary figure 2. mc9s12h-family ?z? version block diagram extal xtal bkgd xirq periodic interrupt cop watchdog clock monitor breakpoints pll xfc irq eclk pa4 pa3 pa2 pa1 pa0 pa7 pa6 pa5 test pb4 pb0 pb7 pb6 fp4 fp3 fp2 fp1 fp0 fp7 fp6 pe4 pe5 pe6 pe0 pe1 ioc2 ioc6 ioc0 ioc7 ioc1 ioc3 ioc4 ioc5 rxd1 txd1 miso mosi ps4 ps5 ps0 ps1 pk3 pk7 pk0 pk1 sck ss ps6 ps7 spi rxcan0 txcan0 pm2 pm3 ddra ddrb pta ptb ddre pte ptk ddrk pts ddrs ptm ddrm pk2 fp12 fp11 fp10 fp9 fp8 fp15 fp14 bp0 bp1 bp2 bp3 fp23 pl3 pl2 pl1 pl0 ddrl ptl fp19 fp18 fp17 fp16 pe7 pe3 pte ddre pe2 fp22 fp21 fp20 vlcd vlcd lcd sci1 can0 modb moda reset vddpll vsspll cpu12 clock and reset generation module ptk ddrk fp13 pb5 pb3 pb2 pb1 fp5 pix0 pix1 pix2 pix3 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 ptt ddrt fp24 fp25 fp26 fp27 an2 an6 an0 an7 an1 an3 an4 an5 pad3 pad4 pad5 pad6 pad7 pad0 pad1 pad2 vrh vrl vdda1,2 vssa1,2 analog to digital converter ddrad vrh vrl vdda vssa 256k, 128k bytes flash eeprom or rom 2k bytes eeprom 12k, 8k, 6k bytes ram multiplexed address/data bus ppage data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 data7 data6 data5 data4 data3 data2 data1 data0 multiplexed wide bus multiplexed narrow bus ecs /romctl xaddr14 xaddr15 xaddr16 xaddr17 noacc/xclks lstrb /taglo r/w vddr vdd1 vss1,2 voltage regulator input capture and output compare timer sda scl iic driver pl7 pl6 pl5 pl4 fp31 fp30 fp29 fp28 system integration module single-wire background debug module rxcan1 txcan1 pm4 pm5 can1 m0c0m m0c0p pu0 pu1 ptu ddru pwm0 ssd0 motor0 and motor1 supply vddm1,2 vssm1,2 m0c1m m0c1p pu2 pu3 pwm1 m1c0m m1c0p pu4 pu5 pwm2 ssd1 m1c1m m1c1p pu6 pu7 pwm3 vddx1,2 vssx1,2 vsspll pll 2.5v i/o driver 5v a/d converter 5v & vddpll vdd1 vss1,2 internal logic 2.5v vdda vssa vddr vreg input 5v supply pins voltage regulator reference pulse width modulator pw2 pw0 pw1 pw3 pw4 pw5 pp3 pp4 pp5 pp0 pp1 pp2 ptp ddrp rxd0 txd0 sci0 an10 an14 an8 an15 an9 an11 an12 an13 an10 an14 an8 an15 an9 an11 an12 an13 kwad2 kwad6 kwad0 kwad7 kwad1 kwad3 kwad4 kwad5 m0cosm m0cosp m0sinm m0sinp m1cosm m1cosp m1sinm m1sinp ptad m2c0m m2c0p pv0 pv1 ptv ddrv pwm4 ssd2 motor2 and motor3 supply vddm2,3 vssm2,3 m2c1m m2c1p pv2 pv3 pwm5 m3c0m m3c0p pv4 pv5 pwm6 ssd3 m3c1m m3c1p pv6 pv7 pwm7 m2cosm m2cosp m2sinm m2sinp m3cosm m3cosp m3sinm m3sinp
16-bit microcontr oller hcs12h family, rev. 11.1 8 freescale semiconductor preliminary pin assignments pin assignments figure 1. 144-pin package si gnal assignments for 9S12H256 m0c0m/pu0 m0c0p/pu1 m0c1m/pu2 m0c1p/pu3 vddm1 vssm1 m1c0m/pu4 m1c0p/pu5 m1c1m/pu6 m1c1p/pu7 kwh0/ph0 kwh1/ph1 kwh2/ph2 kwh3/ph3 m2c0m/pv0 m2c0p/pv1 m2c1m/pv2 m2c1p/pv3 vddm2 vssm2 m3c0m/pv4 m3c0p/pv5 m3c1m/pv6 m3c1p/pv7 kwh4/ph4 kwh5/ph5 kwh6/ph6 kwh7/ph7 m4c0m/pw0 m4c0p/pw1 m4c1m/pw2 m4c1p/pw3 vddm3 vssm3 m5c0m/pw4 m5c0p/pw5 m5c1m/pw6 m5c1p/pw7 pwm0/pp0 pwm1/pp1 pwm2/pp2 pwm3/pp3 pwm4/pp4 pwm5/pp5 rxd0/ps0 txd0/ps1 rxd1/ps2 txd1/ps3 vss2 vddr vddx2 vssx2 modc/taghi /bkgd reset vddpll xfc vsspll extal xtal test sda/pm0 scl/pm1 rxcan0/pm2 txcan0/pm3 rxcan1pm4 txcan1/pm5 moda/ipipe0/pe5 miso/ps4 mosi/ps5 sck/ps6 ss /ps7 irq /pe1 pb5/addr5/data5/fp5 pb4/addr4/data4/fp4 pb3/addr3/data3/fp3 pb2/addr2/data2/fp2 pb1/addr1/data1/fp1 pb0/addr0/data0/fp0 pk0/xaddr14/bp0 pk1/xaddr15/bp1 pk2/xaddr16/bp2 pk3/xaddr17/bp3 vlcd vss1 vdd1 pad15/an15 pad7/an7 pad14/an14 pad6/an6 pad13/an13 pad5/an5 pad12/an12 pad4/an4 pad11/an11 pad3/an3 pad10/an10 pad2/an2 pad9/an9 pad1/an1 pad8/an8 pad0/an0 vdda vrh vrl vssa pe0/xirq pe4/eclk pe6/ipipe1/modb pt7/ioc7 pt6/ioc6 pt5/ioc5 pt4/ioc4 pt3/ioc3/fp27 pt2/ioc2/fp26 pt1/ioc1/fp25 pt0/ioc0/fp24 pj3/kwj3 pj2/kwj2 pj1/kwj1 pj0/kwj0 vssx1 vddx1 pk7/ecs /romctl/fp23 pe7/noacc/xclks/fp22 pe3/lstrb /taglo/ fp21 pe2/r/w /fp20 pl7/fp31 pl6/fp30 pl5/fp29 pl4/fp28 pl3/fp19 pl2/fp18 pl1/fp17 pl0/fp16 pa7/addr15/data15/fp15 pa6/addr14/data14/fp14 pa5/addr13/data13/fp13 pa4/addr12/data12/fp12 pa3/addr11/data11/fp11 pa2/addr10/data10/fp10 pa1/addr9/data9/fp9 pa0/addr8/data8/fp8 pb7/addr7/data7/fp7 pb6/addr6/data6/fp6 9S12H256 144 lqfp pins shown in bold are not available in the 112 qfp package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
pin assignments 16-bit microcontr oller hcs12h family, rev. 11.1 freescale semiconductor 9 preliminary figure 2. 112-pin package signal assignments for 9S12H256, 3s12h256 and 3s12h192 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 9S12H256, 9s12h128, 3s12h256, 3s12h192 112 lqfp 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 m0c0m/pu0 m0c0p/pu1 m0c1m/pu2 m0c1p/pu3 vddm1 vssm1 m1c0m/pu4 m1c0p/pu5 m1c1m/pu6 m1c1p/pu7 m2c0m/pv0 m2c0p/pv1 m2c1m/pv2 m2c1p/pv3 vddm2 vssm2 m3c0m/pv4 m3c0p/pv5 m3c1m/pv6 m3c1p/pv7 m4c0m/pw0 m4c0p/pw1 m4c1m/pw2 m4c1p/pw3 vddm3 vssm3 m5c0m/pw4 m5c0p/pw5 pt7/ioc7 pt6/ioc6 pt5/ioc5 pt4/ioc4 pt3/ioc3/fp27 pt2/ioc2/fp26 pt1/ioc1/fp25 pt0/ioc0/fp24 vssx1 vddx1 pk7/ecs /romctl/fp23 pe7/noacc/xclks/fp22 pe3/lstrb /taglo /fp21 pe2/r/w /fp20 pl3/fp19 pl2/fp18 pl1/fp17 pl0/fp16 pa7/addr15/data15/fp15 pa6/addr14/data14/fp14 pa5/addr13/data13/fp13 pa4/addr12/data12/fp12 pa3/addr11/data11/fp11 pa2/addr10/data10/fp10 pa1/addr9/data9/fp9 pa0/addr8/data8/fp8 pb7/addr7/data7/fp7 pb6/addr6/data6/fp6 pb5/addr5/data5/fp5 pb4/addr4/data4/fp4 pb3/addr3/data3/fp3 pb2/addr2/data2/fp2 pb1/addr1/data1/fp1 pb0/addr0/data0/fp0 pk0/xaddr14/bp0 pk1/xaddr15/bp1 pk2/xaddr16/bp2 pk3/xaddr17/bp3 vlcd vss1 vdd1 pad7/an7 pad6/an6 pad5/an5 pad4/an4 pad3/an3 pad2/an2 pad1/an1 pad0/an0 vdda vrh vrl vssa pe0/xirq pe4/eclk pe6/ipipe1/modb m5c1m/pw6 m5c1p/pw7 pwm0/pp0 pwm1/pp1 rxd0/ps0 txd0/ps1 vss2 vddr vddx2 vssx2 modc/taghi /bkgd reset vddpll xfc vsspll extal xtal test rxcan0/pm2 txcan0/pm3 rxcan1/pm4 txcan1/pm5 moda/ipipe0/pe5 miso/ps4 mosi/ps5 sck/ps6 ss /ps7 irq /pe1
16-bit microcontr oller hcs12h family, rev. 11.1 10 freescale semiconductor preliminary pin assignments figure 3. 112-pin package signal assignments for 9s12hz256, 9s12hz128, 3s12hz128 and 3s12hn128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 9s12hz256, 9s12hz128, 3s12hz128, 3s12hn128 112 lqfp 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 fp28/an12/pl4 fp29an13//pl5 fp30/an14//pl6 fp31/an15/pl7 vddm1 vssm1 m0c0m/m0cosm/pu0 m0c0p/m0cosp/pu1 m0c1m/m0sinm/pu2 m0c1p/m0sinp/pu3 m1c0m/m1cosm/pu4 m1c0p/m1cosp/pu5 m1c1m/m1sinm/pu6 m1c1p/m1sinp/pu7 vddm2 vssm2 m2c0m/m2cosm/pv0 m2c0p/m2cosp/pv1 m2c1m/m2sinm/pv2 m2c1p/m2sinp/pv3 m3c0m/m3cosm/pv4 m3c0p/m3cosp/pv5 m3c1m/m3sinm/pv6 m3c1p/m3sinp/pv7 vddm3 vssm3 scl /pwm5/pp5 sda /pwm4/pp4 pt7/ioc7 pt6/ioc6 pt5/ioc5 pt4/ioc4 pt3/ioc3/fp27 pt2/ioc2/fp26 pt1/ioc1/fp25 pt0/ioc0/fp24 vssx1 vddx1 pk7/ ecs /romctl /fp23 pe7/ noacc /xclks/fp22 pe3/ lstrb /taglo /fp21 pe2/ r/w /fp20 pl3/an11/fp19 pl2/an10/fp18 pl1/an9/fp17 pl0/an8/fp16 pa7/ addr15/data15 /fp15 pa6/ addr14/data14 /fp14 pa5/ addr13/data13 /fp13 pa4/ addr12/data12 /fp12 pa3/ addr11/data11 /fp11 pa2/ addr10/data1 0/fp10 pa1/ addr9/data9 /fp9 pa0/ addr8/data8 /fp8 pb7/ addr7/data7 /fp7 pb6/ addr6/data6 /fp6 pb5/ addr5/data5 /fp5 pb4/ addr4/data4 /fp4 pb3/addr3/data3/fp3 pb2/addr2/data2/fp2 pb1/addr1/data1/fp1 pb0/addr0/data0/fp0 pk0/ xaddr14 /bp0 pk1/ xaddr15 /bp1 pk2/ xaddr16 /bp2 pk3/ xaddr17 /bp3 vlcd vss1 vdd1 pad7/kwad7/an7 pad6/kwad6/an6 pad5/kwad5/an5 pad4/kwad4/an4 pad3/kwad3/an3 pad2/kwad2/an2 pad1/kwad1/an1 pad0/kwad0/an0 vdda vrh vrl vssa pe0/xirq pe4/eclk pe6/ipipe1/modb pwm3/pp3 rxd1/pwm2/pp2 txd1 /pwm0/pp0 pwm1/pp1 rxd0/ps0 txd0/ps1 vss2 vddr vddx2 vssx2 modc/ taghi /bkgd reset vddpll xfc vsspll extal xtal test rxcan0/pm2 txcan0/pm3 rxcan1/pm4 txcan1/pm5 moda/ipipe0/pe5 miso /ps4 mosi /ps5 sck /ps6 ss /ps7 irq /pe1 signals shown in bold are not available in the 80 qfp package
pin assignments 16-bit microcontr oller hcs12h family, rev. 11.1 freescale semiconductor 11 preliminary figure 4. 112-pin package signal assignments for 9s12hz64, 9s12hn64, 3s12hz64 and 3s12hn64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 9s12hz64, 9s12hn64, 3s12hz64, 3s12hn64 112 lqfp 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 nc nc nc nc nc nc m0c0m/m0cosm/pu0 m0c0p/m0cosp/pu1 m0c1m/m0sinm/pu2 m0c1p/m0sinp/pu3 m1c0m/m1cosm/pu4 m1c0p/m1cosp/pu5 m1c1m/m1sinm/pu6 m1c1p/m1sinp/pu7 vddm2 vssm2 m2c0m/m2cosm/pv0 m2c0p/m2cosp/pv1 m2c1m/m2sinm/pv2 m2c1p/m2sinp/pv3 m3c0m/m3cosm/pv4 m3c0p/m3cosp/pv5 m3c1m/m3sinm/pv6 m3c1p/m3sinp/pv7 nc nc pwm5/pp5 pwm4/pp4 pt7/ioc7 pt6/ioc6 pt5/ioc5 pt4/ioc4 pt3/ioc3/fp27 pt2/ioc2/fp26 pt1/ioc1/fp25 pt0/ioc0/fp24 vssx1 vddx1 pk7/fp23 pe7/xclks/fp22 pe3/fp21 pe2/fp20 pl3/fp19 pl2/fp18 pl1/fp17 pl0/fp16 pa7/fp15 pa6/fp14 pa5/fp13 pa4/fp12 pa3/fp11 pa2/fp10 pa1/fp9 pa0/fp8 pb7/fp7 pb6/fp6 pb5/fp5 pb4/fp4 nc nc nc nc pk0/bp0 pk1/bp1 pk2/bp2 pk3/bp3 vlcd vss1 vdd1 pad7/kwad7/an7 pad6/kwad6/an6 pad5/kwad5/an5 pad4/kwad4/an4 pad3/kwad3/an3 pad2/kwad2/an2 pad1/kwad1/an1 pad0/kwad0/an0 vdda nc nc vssa pe0/xirq pe4/eclk nc pwm3/pp3 nc nc pwm1/pp1 rxd0/ps0 txd0/ps1 vss2 nc vddx2 vssx2 modc/bkgd reset vddpll xfc vsspll extal xtal test rxcan0/pm2 txcan0/pm3 nc nc nc miso /ps4 mosi /ps5 sck /ps6 nc nc signals shown in bold are not available in the 80 qfp package
16-bit microcontr oller hcs12h family, rev. 11.1 12 freescale semiconductor preliminary pin assignments figure 5. 80-pin package signal assignments fo r 9s12hz64, 9s12hn64, 3s12hz32 and 3s12hn32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 9s12hz64, 9s12hn64, 3s12hz32, 3s12hn32 80 qfp pb5/fp5 pb4/fp4 pk0/xaddr14/bp0 pk1/xaddr15/bp1 pk2/xaddr16/bp2 pk3/xaddr17/bp3 vlcd vss1 vdd1 pad6/kwad6/an6 pad5/kwad5/an5 pad4/kwad4/an4 pad3/kwad3/an3 pad2/kwad2/an2 pad1/kwad1/an1 pad0/kwad0/an0 vdda vssa pe0/xirq pe4/eclk pt3/ioc3/fp27 pt2/ioc2/fp26 pt1/ioc1/fp25 pt0/ioc0/fp24 vssx1 vddx1 pk7/fp23 pe7/xclks/fp22 pe3/fp21 pe2/fp20 pa7/fp15 pa6/fp14 pa5/fp13 pa4/fp12 pa3/fp11 pa2/fp10 pa1/fp9 pa0/fp8 pb7/fp7 pb6/fp6 m0c0m/m0cosm/pu0 m0c0p/m0cosp/pu1 m0c1m/m0sinm/pu2 m0c1p/m0sinp/pu3 m1c0m/m1cosm/pu4 m1c0p/m1cosp/pu5 m1c1m/m1sinm/pu6 m1c1p/m1sinp/pu7 vddm2 vssm2 m2c0m/m2cosm/pv0 m2c0p/m2cosp/pv1 m2c1m/m2sinm/pv2 m2c1p/m2sinp/pv3 m3c0m/m3cosm/pv4 m3c0p/m3cosp/pv5 m3c1m/m3sinm/pv6 m3c1p/m3sinp/pv7 pwm5/pp5 pwm4/pp4 pwm3/pp3 pwm1/pp1 rxd0/ps0 txd0/ps1 vss2 vddx2 vssx2 modc/bkgd reset vddpll xfc vsspll extal xtal test rxcan0/pm2 txcan0/pm3 ps4 ps5 ps6 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
pin assignments 16-bit microcontr oller hcs12h family, rev. 11.1 freescale semiconductor 13 preliminary table 2 pin descriptions note: features shown in bold are not available in the 9S12H256 112 pin qfp package. note: features shown in italics are only available for the ?z? versions pin name function 1 pin name function 2 pin name function 3 pin name function 4 description extal ?? ? crystal driver and external clock input pins. on reset all the device clocks are derived from the extal input frequency. xtal is the crystal output xtal ?? ? reset ?? ? active low bidirectional control si gnal that acts as an input to initialize the mcu to a known st art-up state, and an output when an internal mcu function causes a reset. test ?? ? test input bkgd taghi modc ? function 1: pseudo-open-drai n communication pin for the background debug function. function 2: in mcu expanded modes of operation when in- struction tagging is on, an input low on this pin during the falling edge of e-clock tags the high half of the instruction word being read into the instruction queue. function 3: at the rising edge duri ng reset, the state of this pin is latched to the modc bit to set the mcu operating mode. pad[15:8] an[15:8] ?? function 1: port ad general purpose inputs function 2: analog inputs (atd) pad[7:0] an[7:0] kwad[7:0] ? function 1: port ad general purpose inputs function 2: analog inputs (atd) function 3: key wake-up input pins that can generate an inter- rupt causing the mcu to exit stop or wait mode. pa[7:0] fp[15:8] addr[15:8]/d ata[15:8] ? function 1: port a general purpose input or output pins. function 2: lcd frontplane segment driver output pin. function 3: in mcu expanded modes of operation, these pins are used for the multiplexed external address and data bus. pb[7:0] fp[7:0] addr[7:0]/da ta[7:0] ? function 1: port b general purpose input or output pins. function 2: lcd frontplane segment driver output pin. function 3: in mcu expanded modes of operation, these pins are used for the multiplexed external address and data bus. pe7 fp22 xclks noacc function 1: port e general purpose input or output pin function 2: lcd frontplane segment driver output pin function 3: the xclks signal selects between an external clock or oscillator configuration during reset. this pin should be at a logic high during reset if an external clock is used on the extal input pin. this pin should be at a logic low during reset if an oscillator circuit is configured on extal and xtal. since this pin is an input with a pull-down device during reset, if the pin is left floating, the default configuration is an oscillator circuit on extal and xtal. function 4: during mcu expanded modes of operation, the noacc signal, when enabled, is used to indicate that the current bus cycle is an unused or ?free? cycle. this signal will assert when the cpu is not using the bus.
16-bit microcontr oller hcs12h family, rev. 11.1 14 freescale semiconductor preliminary pin assignments pe6 ipipe1 modb ? function 1: port e general purpose input or output pins. function 2: instruction queue tracking signals. function 3: the state of the moda and modb pins during reset determine the initial operating mode of the mcu pe5 ipipe0 moda ? pe4 eclk ?? function 1: port e general purpose input or output pin. function 2: internal bus clock ou tput that can be used as a tim- ing reference. pe3 fp21 lstrb taglo function 1: port e general purpose input or output pin. function 2: lcd frontplane segment driver output pin. function 3: in mcu expanded modes of operation, lstrb is used for the low-byte strobe function to indicate the type of bus access. function 4: when instruction tagging is on, taglo is used to tag the low half of the instru ction word being read into the instruction queue. pe2 fp20 r/w ? function 1: port e general purpose input or output pin. function 2: lcd frontplane segment driver output pin. function 3: in mcu expanded modes of operations, performs the read/write output signal for the external bus. this pin indicates direction of data on the external bus. pe1 irq ?? function 1: port e general purpose input pin. function 2: maskable interrupt request input provides a means of applying asynchronous interrupt requests. will wake up the mcu from stop or wait mode pe0 xirq ?? function 1: port e general purpose input pin. function 2: nonmaskable interrupt request input provides a means of applying asynchronous interrupt requests. will wake up the mcu from stop or wait mode. ph[7:0] kwh[7:0] ?? function 1: port h general purpose input or output pins. function 2: key wake-up input pins that can generate an interrupt causing the mcu to exit stop or wait mode. pj[3:0] kwj[3:0] ?? function 1: port j general purpose input or output pins. function 2: key wake-up input pins that can generate an interrupt causing the mcu to exit stop or wait mode. pk7 fp23 ecs romctl function 1: port k general purpose input or output pin. function 2: lcd frontplane segment driver output pin. function 3: during mcu expanded modes of operation, this pin is used to enable the flash eeprom memory in the memory map. function 4: during mcu expanded modes of operation, this pin is used as the emulation chip select signal. pk[3:0] bp[3:0] xaddr[17:14] ? function 1: port k general purpose input or output pins. function 2: lcd backplane segment driver output pins. function 3: in mcu expanded modes of operation, expanded address pins for the external bus. pl[7:4] fp[31:28] an[15:12] ? function 1: port l general purpose input or output pins. function 2: lcd frontplane segment driver output pins. function 3: analog inputs (atd). table 2 pin descriptions note: features shown in bold are not available in the 9S12H256 112 pin qfp package. note: features shown in italics are only available for the ?z? versions pin name function 1 pin name function 2 pin name function 3 pin name function 4 description
pin assignments 16-bit microcontr oller hcs12h family, rev. 11.1 freescale semiconductor 15 preliminary pl[3:0] fp[19:16] an[11:08] ? function 1: port l general purpose input or output pins. function 2: lcd frontplane s egment driver output pins. function 3: analog inputs (atd). pm5 txcan1 ?? function 1: port m general purpose input or output pin. function 2: transmit pin for the motorola scalable controller area network controller 1 (mscan1). pm4 rxcan1 ?? function 1: port m general purpose input or output pin. function 2: receive pin for the motorola scalable controller area network controller 1 (mscan1). pm3 txcan0 ?? function 1: port m general purpose input or output pin. function 2: transmit pin for the motorola scalable controller area network controller 0 (mscan0). pm2 rxcan0 ?? function 1: port m general purpose input or output pin. function 2: receive pin for the motorola scalable controller area network controller 0 (mscan0). pm1 scl ?? function 1: port m general purpose input or output pin. function 2: serial clock pin for the inter-ic bus interface (iic). pm0 sda ?? function 1: port m general purpose input or output pin. function 2: serial data pin for the inter-ic bus interface (iic). pp5 pwm5 scl ? function 1: port p general purpose input or output pins. function 2: pulse width modu lator (pwm) channel output pins. function 3: serial clock pin for the inter-ic bus interface (iic). pp4 pwm4 sda ? function 1: port p general purpose input or output pins. function 2: pulse width modu lator (pwm) channel output pins. function 3: serial data pin for the inter-ic bus interface (iic). pp3 pwm3 ?? function 1: port p general purpose input or output pins. function 2: pulse width modu lator (pwm) channel output pins. function 3: transmit pin of serial communication interface 1 (sci1). pp2 pwm2 rxd1 ? function 1: port p general purpose input or output pins. function 2: pulse width modu lator (pwm) channel output pins. function 3: receive pin of serial communication interface 1 (sci1). pp1 pwm1 ?? function 1: general pur pose input or output pin. function 2: pulse width modulat or (pwm) channel output pin. pp0 pwm0 txd1 ? function 1: general pur pose input or output pin. function 2: pulse width modulat or (pwm) channel output pin. function 3: transmit pin of serial communication inter- face 1 (sci1). table 2 pin descriptions note: features shown in bold are not available in the 9S12H256 112 pin qfp package. note: features shown in italics are only available for the ?z? versions pin name function 1 pin name function 2 pin name function 3 pin name function 4 description
16-bit microcontr oller hcs12h family, rev. 11.1 16 freescale semiconductor preliminary pin assignments ps7 ss ?? function 1: port s general purpose input or output pin. function 2: slave select pin for the serial peripheral interface (spi). ps6 sck ?? function 1: port s general purpose input or output pin. function 2: serial clock pin for the serial peripheral interface (spi). ps5 mosi ?? function 1: port s general purpose input or output pin. function 2: master output (during master mode) or slave input (during slave mode) pin for the serial peripheral interface (spi). ps4 miso ?? function 1: port s general purpose input or output pin. function 2: master input (durin g master mode) or slave output (during slave mode) pin for the serial peripheral interface (spi). ps3 txd1 ?? function 1: port s general purpose input or output pin. function 2: transmit pin of serial communication interface 1 (sci1). ps2 rxd1 ?? function 1: port s general purpose input or output pin. function 2: receive pin of serial communication interface 1 (sci1). ps1 txd0 ?? function 1: port s general purpose input or output pin. function 2: transmit pin of serial communication interface 0 (sci0). ps0 rxd1 ?? function 1: port s general purpose input or output pin. function 2: receive pin of serial communication interface 0 (sci0). pt[7:4] ioc[7:4] ?? function 1: port t general purpose input or output pins. function 2: timer input capt ure or output compare pins. pt[3:0] ioc[3:0] fp[27:24] ? function 1: port t general purpose input or output pins. function 2: timer input capt ure or output compare pins. function 3: lcd frontplane s egment driver output pins. pu7 m1c1p ?? function 1: port u general pu rpose input or output pins. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 1. pwm output on m1c1m results in a positive current flow through coil 1 when m1c1p is driven to a logic high state. pu6 m1c1m ?? pu5 m1c0p ?? function 1: port u general pu rpose input or output pins. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 1. pwm output on m1c0m results in a positive current flow through coil 0 when m1c0p is driven to a logic high state. pu4 m1c0m ?? pu3 m0c1p ?? function 1: port u general pu rpose input or output pins. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 0. pwm output on m0c1m results in a positive current flow through coil 1 when m0c1p is driven to a logic high state. pu2 m0c1m ?? table 2 pin descriptions note: features shown in bold are not available in the 9S12H256 112 pin qfp package. note: features shown in italics are only available for the ?z? versions pin name function 1 pin name function 2 pin name function 3 pin name function 4 description
pin assignments 16-bit microcontr oller hcs12h family, rev. 11.1 freescale semiconductor 17 preliminary pu1 m0c0p ?? function 1: port u general pu rpose input or output pins. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 0. pwm output on m0c0m results in a positive current flow through coil 0 when m0c0p is driven to a logic high state. pu0 m0c0m ?? pv7 m3c1p ?? function 1: port v general purpose input or output pins. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 3. pwm output on m3c1m results in a positive current flow through coil 1 when m3c1p is driven to a logic high state. pv6 m3c1m ?? pv5 m3c0p ?? function 1: port v general purpose input or output pins. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 3. pwm output on m3c0m results in a positive current flow through coil 0 when m3c0p is driven to a logic high state. pv4 m3c0m ?? pv3 m2c1p ?? function 1: port v general purpose input or output pins. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 2. pwm output on m2c1m results in a positive current flow through coil 1 when m2c1p is driven to a logic high state. pv2 m2c1m ?? pv1 m2c0p ?? function 1: port v general purpose input or output pins. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 2. pwm output on m2c0m results in a positive current flow through coil 0 when m2c0p is driven to a logic high state. pv0 m2c0m ?? pw7 m5c1p ?? function 1: port w general purpose input or output pins. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 5. pwm output on m5c1m results in a positive current flow through coil 1 when m5c1p is driven to a logic high state. pw6 m5c1m ?? pw5 m3c0p ?? function 1: port w general purpose input or output pins. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 5. pwm output on m5c0m results in a positive current flow through coil 0 when m5c0p is driven to a logic high state. pw4 m5c0m ?? pw3 m4c1p ?? function 1: port w general purpose input or output pins. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 4. pwm output on m4c1m results in a positive current flow through coil 1 when m4c1p is driven to a logic high state. pw2 m4c1m ?? pw1 m4c0p ?? function 1: port w general purpose input or output pins. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 4. pwm output on m4c0m results in a positive current flow through coil 0 when m4c0p is driven to a logic high state. pw0 m4c0m ?? vlcd ?? ? supply input pin for the lcd driver. adjusting the voltage on this pin will change the display contrast. table 2 pin descriptions note: features shown in bold are not available in the 9S12H256 112 pin qfp package. note: features shown in italics are only available for the ?z? versions pin name function 1 pin name function 2 pin name function 3 pin name function 4 description
16-bit microcontr oller hcs12h family, rev. 11.1 18 freescale semiconductor preliminary pin assignments vdda ?? ? supply input pins for the voltage regulator and the analog to digital converter. tolerance = 5v 5%. vssa ?? ? vrh ?? ? reference voltage input pins for the analog to digital converter. vrl ?? ? vddm1 ?? ? supply input pins for motor 0 and motor 1 output drivers. tolerance = 5 v 10%. vssm1 ?? ? vddm2 ?? ? supply input pins for motor 2 and motor 3 output drivers. tolerance = 5 v 10%. vssm2 ?? ? vddm3 ?? ? supply input pins for motor 4 and motor 5 output drivers. tolerance = 5 v 10%. vssm3 ?? ? vddpll ?? ? pll supply output pins. no load allowed except for bypass capacitors. vsspll ?? ? vddx1 ?? ? supply input pins for input/o utput drivers. tolerance = 5v 5%. vssx1 ?? ? vddx2 ?? ? vssx2 ?? ? vdd1 ?? ? core supply output pins. no load allowed except for bypass capacitors. vss1 ?? ? vss2 ?? ? vddr ?? ? power supply input pin for voltage regulator. nominal 5v table 2 pin descriptions note: features shown in bold are not available in the 9S12H256 112 pin qfp package. note: features shown in italics are only available for the ?z? versions pin name function 1 pin name function 2 pin name function 3 pin name function 4 description
memory maps 16-bit microcontr oller hcs12h family, rev. 11.1 freescale semiconductor 19 preliminary memory maps figure 6. mc9(3)s12h256 user configurable memory map $0000 $ffff $c000 $8000 $4000 $0400 $1000 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window sixteen * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 0.5k, 1k, 2k or 4k protected sector $1000 $3fff $0000 $0fff 4k bytes eeprom mappable to any 4k boundary $0000 $03ff 1k register space mappable to any 2k boundary mappable to any 16k boundary 12k bytes ram alignable to top ($1000 - $3fff) or bottom ($0000 - $2fff) initially overlapped by register space the figure shows a useful map, which is not the map out of reset. after reset the map is: $0000 - $03ff: register space $1000 - $3fff: 12k ram for mc9S12H256 there is no mapping of eeprom flash on mc3s12h256. $0000 - $0fff: 4k eeprom (1k not visible) on mc9S12H256 only.
16-bit microcontr oller hcs12h family, rev. 11.1 20 freescale semiconductor preliminary memory maps figure 7. mc9(3)s12hz256 user configurable memory map $0000 $ffff $c000 $8000 $4000 $0400 $0800 $1000 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window sixteen * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 0.5k, 1k, 2k or 4k protected sector $1000 $3fff 12k bytes ram mappable to any16k boundary $0800 $0fff 2k bytes eeprom mappable to any 2k boundary $0000 $03ff 1k register space mappable to any 2k boundary the figure shows a useful map, which is not t he map out of reset. after reset the map is: $0000 - $03ff: register space $1000 - $3fff: 12k ram $0000 - $07ff: 2k eepr om (1k not visible) there is no mapping of eepr om flash on mc3s12hz256.
memory maps 16-bit microcontr oller hcs12h family, rev. 11.1 freescale semiconductor 21 preliminary figure 8. mc3s12hz192 user configurable memory map $0000 $ffff $c000 $8000 $4000 $0400 $2000 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window twelve * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 0.5k, 1k, 2k or 4k protected sector $2000 $3fff 8k bytes ram mappable to any 8k boundary $0000 $03ff 1k register space mappable to any 2k boundary the figure shows a useful map, which is not t he map out of reset. after reset the map is: $0000 - $03ff: register space $0000 - $1fff: 8k ram (1k not visible)
16-bit microcontr oller hcs12h family, rev. 11.1 22 freescale semiconductor preliminary memory maps figure 9. mc9(3)s12hz(n)128 user configurable memory map $0000 $ffff $c000 $8000 $4000 $0400 $2800 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window eight * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 0.5k, 1k, 2k or 4k protected sector $2800 $3fff 6k bytes ram mappable to any 8k boundary $0000 $03ff 1k register space mappable to any 2k boundary alignable to top ($2800 - $3fff) or bottom ($2000 - $37ff) of 8k boundary the figure shows a useful map, which is not t he map out of reset. after reset the map is: $0000 - $03ff: register space $0800 - $1fff: 6k ram $0800 $1000 $0800 $0fff 2k bytes eeprom mappable to any 2k boundary $0000 - $07ff: 2k eepr om (1k not visible) there is no mapping of eeprom flash on mc3s12hz(n)128.
memory maps 16-bit microcontr oller hcs12h family, rev. 11.1 freescale semiconductor 23 preliminary figure 10. mc9(3)s12hz(n)64 user configurable memory map $0000 $ffff $c000 $8000 $4000 $3000 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window four * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 0.5k, 1k, 2k or 4k protected sector $3000 $3fff 4k bytes ram mappable to any 4k boundary $0000 $03ff 1k register space mappable to any 2k boundary the figure shows a useful map, which is not t he map out of reset. after reset the map is: $0000 - $03ff: register space $0000 - $0fff: 4k ram (1k not visible) $0400 $0800 $1000 $0800 $0fff 1k bytes eeprom mappable to any 2k boundary (1k mapped twice in 2k boundary) $0000 - $07ff: 1k eeprom ma pped twice (not visible) there is no mapping of eepr om flash on mc3s12hz(n)64
16-bit microcontr oller hcs12h family, rev. 11.1 24 freescale semiconductor preliminary memory maps figure 11. mc3s12hz(n)32 user configurable memory map $0000 $ffff $c000 $8000 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k fixed flash eeprom $0000 $03ff 1k register space mappable to any 2k boundary the figure shows a useful map, which is not t he map out of reset. after reset the map is: $0000 - $03ff: register space $0800 - $0fff: 2k ram $0400 $0800 $1000 $0800 $0fff 2k bytes ram mappable to any 2k boundary
mechanical package dimensions 16-bit microcontr oller hcs12h family, rev. 11.1 freescale semiconductor 25 preliminary mechanical package dimensions figure 3. 144-pin lqfp mechanical dimensions (case no. 918-03) n 0.20 t l-m 144 gage plane 73 109 37 seating 108 1 36 72 plane 4x 4x 36 tips pin 1 ident view y b b1 v1 a1 s1 v p g a s 0.1 c 2 view ab j1 j1 140x 4x view y plating f aa j d base metal section j1-j1 (rotated 90 ) 144 pl n 0.08 m tl-m dim a min max 20.00 bsc millimeters a1 10.00 bsc b 20.00 bsc b1 10.00 bsc c 1.40 1.60 c1 0.05 0.15 c2 1.35 1.45 d 0.17 0.27 e 0.45 0.75 f 0.17 0.23 g 0.50 bsc j 0.09 0.20 k 0.50 ref p 0.25 bsc r1 0.13 0.20 r2 0.13 0.20 s 22.00 bsc s1 11.00 bsc v 22.00 bsc v1 11.00 bsc y 0.25 ref z 1.00 ref aa 0.09 0.16 0 0 7 11 13 1 2 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m, n to be determined at the seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane h. 6. dimension d does not include dambar protrusion. allowable 0.05 c l (z) r2 e c2 (y) r1 (k) c1 1 0.25 view ab n 0.20 t l-m m l n 2 t t 144x x
16-bit microcontr oller hcs12h family, rev. 11.1 26 freescale semiconductor preliminary mechanical package dimensions figure 4. 112-pin lqfp mechanical dimensions (case no. 987) dim a min max 20.000 bsc millimeters a1 10.000 bsc b 20.000 bsc b1 10.000 bsc c --- 1.600 c1 0.050 0.150 c2 1.350 1.450 d 0.270 0.370 e 0.450 0.750 f 0.270 0.330 g 0.650 bsc j 0.090 0.170 k 0.500 ref p 0.325 bsc r1 0.100 0.200 r2 0.100 0.200 s 22.000 bsc s1 11.000 bsc v 22.000 bsc v1 11.000 bsc y 0.250 ref z 1.000 ref aa 0.090 0.160 11 11 13 7 13 view y l-m 0.20 n t 4x 4x 28 tips pin 1 ident 1 112 85 84 28 57 29 56 b v v1 b1 a1 s1 a s view ab 0.10 3 c c2 2 0.050 seating plane gage plane 1 view ab c1 (z) (y) e (k) r2 r1 0.25 j1 view y j1 p g 108x 4x section j1-j1 base rotated 90 counterclockwise metal j aa f d l-m m 0.13 n t 1 2 3 c l l-m 0.20 n t l n m t t 112x x x=l, m or n r r notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m and n to be determined at seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable 8 3 0
mechanical package dimensions 16-bit microcontr oller hcs12h family, rev. 11.1 freescale semiconductor 27 preliminary figure 5. 80-pin qfp mechanical dimensions (case no. 841b) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -a-, -b- and -d- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -c-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. section b-b 61 60 detail a l 41 40 80 -a- l -d- a s a-b m 0.20 d s h 0.05 a-b s 120 21 -b- b v j f n d view rotated 90 detail a b b p -a-,-b-,-d- e h g m m detail c seating plane -c- c datum plane 0.10 -h- datum plane -h- u t r q k w x detail c dim min max millimeters a 13.90 14.10 b 13.90 14.10 c 2.15 2.45 d 0.22 0.38 e 2.00 2.40 f 0.22 0.33 g 0.65 bsc h --- 0.25 j 0.13 0.23 k 0.65 0.95 l 12.35 ref m 5 10 n 0.13 0.17 p 0.325 bsc q 0 7 r 0.13 0.30 s 16.95 17.45 t 0.13 --- u 0 --- v 16.95 17.45 w 0.35 0.45 x 1.6 ref s a-b m 0.20 d s c s a-b m 0.20 d s h 0.05 d s a-b m 0.20 d s c s a-b m 0.20 d s c
s12hfampp rev. 11.1, 17-aug-2004 how to reach us: usa/europe/locations not listed: freescale semiconductor literature distribution p.o. box 5405, denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: freescale semiconductor japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: freescale semiconductor h.k. ltd. 2 dai king street tai po industrial estate tai po, n.t. hong kong 852-26668334 learn more: for more information about freescale semiconductor products, please visit http://www.freescale.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale se miconductor assume any liability arising out of the application or use of any product or circuit, and sp ecifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor dat a sheets and/or specifications can and do vary in different applications and actual performa nce may vary over time. all operating parameters, including ?typicals? must be validat ed for each customer application by customer?s technical experts. freescale semiconductor does not conv ey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such uni ntended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any cl aim of personal injury or death associated with such unintended or unauthorized use, even if such cl aim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2004. preliminary

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